OK, so you want to compute some function that is presented as a (constant) table lookup on 64-bit integers, for example. We have a simple which is 2^64 entries of 64-bits each. This can be done using a ROM, which is usually laid out as an approximate square on a chip, so we have 64 square tables each (2^32)x(2^32), or an 8x8 array of such tables, or a single table (2^35)x(2^35). Even today, this is a monster chip (113'x113' -- the footprint of a large mansion or a small hotel) at nanometer feature sizes. But if the function is quite smooth & multiply differentiable -- e.g., a typical arithmetic function, we should be able to dramatically reduce this size to something reasonable. We can use various piecewise interpolation techniques and trade off huge amounts of area for very modest increases in circuit depth. If we're quite lucky, we might even be able to use a table for a 2-argument function -- e.g., f(x,y)=x*y. The "Chebfun" system (www.chebfun.org) uses Chebyshev polynomials to dramatically reduce the effort for representing arbitrary functions with, e.g., 20-30 points instead of 1,000,000. So something like Chebfun might be used to mechanically compute a table lookup chip of reasonable size. Has anyone in academia (or anywhere else) gone into the business of accepting a large table of function values over the Internet and delivering an optimized chip for that function?