[math-fun] Intel to incorporate FPGA in new Xeon processor
So I see (at least) three types of work the FPGA could do:
1. Complicated work on small data---bitcoin mining and stuff like that. FPGAs tend to do this well; no latency concerns or memory access bottlenecks.
2. Streaming work. Will the FPGA have a streamable interface to the memory hierarchy? If so, all sorts of vector work with big computations are possible. It becomes SSE on steroids (of course subject to memory bandwidth limitations).
3. Random access work. Will the FPGA have random access to the memory hierarchy? And if so, how many memory accesses could be in flight at one time? This would permit another wide range of possible applications.
I don't have high expectations for the first iteration of this
--well, for example, consider the "deep blue" chess machine. Would you be able to build it in a FPGA? If so, you'd get a huge performance boost for chess programs. --for another example, suppose you are writing a SAT solver. It seems obvious (?) an FPGA could vastly speed it up. --Let's say we want to make a Lehmer-style sieve for scanning thru integers seeking one which obeys some large set of simultaneous congruences, for example you want to find N such that N is a square modulo the first J primes (but not square). I would expect these three tasks would obtain factor 100 speedups. No?
I'd actually be a bit surprised if any of these three could see significant (>10x) speedups through integration of a single FPGA on a processor die. Perhaps the FPGA might be 10x or more faster than the straightforward churn through all possibilities, but I suspect more advanced methods may make use of more memory (pattern databases, graph structures for the SAT case, etc.) and the FPGA probably would not have a magically faster pipe to memory than the CPU does. On Mon, Jun 23, 2014 at 11:57 AM, Warren D Smith <warren.wds@gmail.com> wrote:
So I see (at least) three types of work the FPGA could do:
1. Complicated work on small data---bitcoin mining and stuff like that. FPGAs tend to do this well; no latency concerns or memory access bottlenecks.
2. Streaming work. Will the FPGA have a streamable interface to the memory hierarchy? If so, all sorts of vector work with big computations are possible. It becomes SSE on steroids (of course subject to memory bandwidth limitations).
3. Random access work. Will the FPGA have random access to the memory hierarchy? And if so, how many memory accesses could be in flight at one time? This would permit another wide range of possible applications.
I don't have high expectations for the first iteration of this
--well, for example, consider the "deep blue" chess machine. Would you be able to build it in a FPGA? If so, you'd get a huge performance boost for chess programs.
--for another example, suppose you are writing a SAT solver. It seems obvious (?) an FPGA could vastly speed it up.
--Let's say we want to make a Lehmer-style sieve for scanning thru integers seeking one which obeys some large set of simultaneous congruences, for example you want to find N such that N is a square modulo the first J primes (but not square).
I would expect these three tasks would obtain factor 100 speedups. No?
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participants (2)
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Tom Rokicki -
Warren D Smith