I think this is a superb development, I've felt that should happen for a long time. It also will address a lot of issues that others (e.g. Jorg Arndt) have been complaining about for years, e.g. "why doesn't my processor have a 'reverse bit order' instruction?" This will be a hacker renaissance. It does not bother me the slightest bit that there is a big pre-wired processor accompanying the FPGA. The stuff lots of users often want, should be available hardwired for speed, not programmable for slowness. Furthermore, in the event that some FPGA use becomes commonplace idiom, that will hopefully inspire the hardware guys to make it available without the FPGA. My question would be: how should a high level language take advantage of this new hardware capability?