Just two remarks and a question about the sand piles. See https://oeis.org/A249872 for the number of moves to reach a steady state. This is independent of the way the updates are made. Q: is the final configuration also always the same? This is a nice problem to do on an FPGA: as expected, the performance is very good, for the 1000 x 1000 instance wall clock time is about 40 times that of a modern CPU and the number of cycles spend is less by a factor of 3000. This is a nice student project IMO (the student needs to be experienced with FPGA design). Best regards, jj * James Propp <jamespropp@gmail.com> [Jul 15. 2017 16:52]:
[...] Read more: https://mathenchant.wordpress.com?p=1784&shareadraft=59690647cdd0e
Thanks,
Jim _______________________________________________ math-fun mailing list math-fun@mailman.xmission.com https://mailman.xmission.com/cgi-bin/mailman/listinfo/math-fun