If you check these patents, you’ll see that we envisioned the FPGA logic having direct read/write access to the processor register files. This would allow an easy single cycle instruction of the kind you envision. Intel probably didn’t do this, although there is nothing difficult about it. US 5,742,180 and US 6,052,773 On Jun 23, 2014, at 1:28 PM, Tom Rokicki <rokicki@gmail.com> wrote:
I suspect the latency of accessing the FPGA may preclude use for single-instruction-type things (like finding the index of the 3rd set bit in a 64-bit word, often used in succinct data structures). I believe the FPGA will be more useful in a coprocessor sense.
It will be interesting to see how the FPGA ties in to the memory hierarchy, if it does at all.
On Mon, Jun 23, 2014 at 10:17 AM, Warren D Smith <warren.wds@gmail.com> wrote:
I think this is a superb development, I've felt that should happen for a long time. It also will address a lot of issues that others (e.g. Jorg Arndt) have been complaining about for years, e.g. "why doesn't my processor have a 'reverse bit order' instruction?" This will be a hacker renaissance.
It does not bother me the slightest bit that there is a big pre-wired processor accompanying the FPGA. The stuff lots of users often want, should be available hardwired for speed, not programmable for slowness.
Furthermore, in the event that some FPGA use becomes commonplace idiom, that will hopefully inspire the hardware guys to make it available without the FPGA.
My question would be: how should a high level language take advantage of this new hardware capability?
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