Power consumption per unit area, partially due to 'leakage current' from transistors which are 'turned off', is currently one of the largest problems at the highest levels of integration. So, yes, real estate -- per se -- is not quite as big of a deal, although it is still very expensive. At 10:00 PM 12/5/02 -0500, Allan C. Wechsler wrote:
At 10:03 AM 11/30/02 -0500, Tom Knight wrote:
A 3-metabit counter begins to count like this:
10 10 10 10 10 01 10 01 10 10 01 01
This is a very common strategy in current generation (hardware) logic design, where certain logic styles such as domino logic allow only monotonic logic functions. Using so-called "dual rail" logic, representing each bit in both possible polarities, and generating, at each stage, both possible polarities, allows this to be a general logic family (with speed advantages). There is no need for negation, of course, since one can choose the polarity of any signal arbitrarily.
This is very cool. I suppose that advances in fabrication techniques mean that we are not as obsessive about chip real estate as we used to be. Using this protocol, it is not only the case that inverters take zero area, but also AND and OR gates are essentially identical.
There are other important reasons to use dual rail logic -- one which the group might appreciate is to reduce the data-dependent noise in cryptographic processors. When the same number of bits go up as down, it is much more difficult to look at e.g. power supply current to determine what the processor is doing. More mundanely, dual rail logic is very good in reducing electromagnetic interference, and, with differential receivers, very resistant to noise.
I wonder if it simplifies power supply design to have the total amount of drawn current vary so little.
-A