April 2018 - mathfun@mailman.xmission.com

[math-fun] model of wallis's integrals...
by françois mendzina essomba2 28 Apr '18

28 Apr '18

Hello J[0]=integrate((qin(x))^(0), x= 0..sigma/2); J[0]=sigma/2 J[1]=integrate(qin(x),x=0..sigma/2) ; J[3]=integrate((qin(x))^(3), x= 0.. sigma/2)=1; On the model of the wallis's integrals. We will have: J[n]=integrate((qin(x))^(n), x= 0..sigma/2); By integration by part: J[n]=integrate((qin(x))^(n-3)*(qin(x))^(3), x, 0, sigma/2); Let : u = (qin(x))^(n-3) ; u’=(n-3)*(qos(x))^(3)* (qin(x))^(n-4) ; v’=(qin(x))^3 ; v=-qos(x) ; We are getting : J[n]=[-(qos(sigma/2))* (qin(sigma/2))^(n-3)+(qos(0))* (qin(0))^(n-3)] + (n-3)* integrate((qin(x))^(n-4)*(qos(x))^(4), x=0..sigma/2); [-(qos(sigma/2))* (qin(sigma/2))^(n-3)+(qos(0))* (qin(0))^(n-3)]=0 because qos(sigma/2)=0 and qin(0)=0 ; >From where : J[n]= (n-3)* integrate((qin(x))^(n-4)*(qos(x))^(4), x=0..sigma/2); Which gives us : J[n]= (n-3)* integrate((qin(x))^(n-4)*(1-(qin(x))^(4)), x=0..sigma/2) = (n-3)* integrate((qin(x))^(n-4)-(qin(x))^(n),x=0.. sigma/2); Which leads us to: J[n]=(n-3)* J[n-4]-(n-3)* J[n] And finally to: J[n]=((n-3)/(n-2))* J[n-4] Since the function is level 4, we will write: J[4n]=((4n-3)/(4n-2))* J[4n-4] ; J[4n+1]=((4n-2)/(4n-1))* J[4n-3] ; J[4n+2]=((4n-1)/(4n))* J[4n-2] ; J[4n+3]=((4n)/(4n+1))* J[4n-1] ; FME...

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[math-fun] "long tail" number notations?
by Henry Baker 27 Apr '18

27 Apr '18

Are there any number notations that aren't *based*, in the sense that one digit doesn't represent O(1/|b|) of the next higher-order digit, where b is the "base" ? I'm particularly looking for notations which *don't* converge quickly. This may sound silly, but why bother with a notation that converges more quickly than series you're trying to represent?

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[math-fun] limited development of some special functions
by françois mendzina essomba2 27 Apr '18

27 Apr '18

I noticed an error in my last post correction of derivations diff(qanh(x),x)=1/(qosh(x))^2;diff(cqnh(x),x)=-1/(qinh(x))^2; limited development of functions to order 16; I found qosh(x)=1+(1/4)*x^4+(9/160)*x^8+(149/9600)*x^(12)+(15147/3328000)*x^16; qinh(x)=x+(3/20)*x^5+(19/480)*x^9+(469/41600)*x^13+(189611/56576000)*x^17; I deduce without verifying that: qos(x)=1-(1/4)*x^4+(9/160)*x^8-(149/9600)*x^(12)+(15147/3328000)*x^16; qin(x)=x-(3/20)*x^5+(19/480)*x^9-(469/41600)*x^13+(189611/56576000)*x^17;

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[math-fun] Special functions
by françois mendzina essomba2 26 Apr '18

26 Apr '18

hello, referring me to sinusoidal functions i write: (qos(x))^4+(qin(x))^4=1;(qosh(x))^4-(qinh(x))^4=1; compound functions: qan(x)=qin(x)/qos(x); cqn(x)=qos(x)/qin(x); qanh(x)=qinh(x)/qosh(x); cqnh(x)=qosh(x)/qinh(x); derivates diff(qos(x),x)=-(qin(x))^3; diff(qin(x),x)=(qos(x))^3; diff(qosh(x),x)=(qinh(x))^3; diff(qinh(x),x)=(qosh(x))^3; diff(qan(x),x)=1/(qos(x))^2; diff(cqn(x),x)=-1/(qin(x))^2; diff(qanh(x),x)=1/(qos(x))^2; diff(cqnh(x),x)=-1/(qin(x))^2; reciprocal functions: aqos(x)=-integrate(1/(1-x^4)^(3/4), x); aqin(x)=integrate(1/(1-x^4)^(3/4), x); aqosh(x)=integrate(1/(x^4-1)^(3/4), x); aqinh(x)=integrate(1/(1+x^4)^(3/4), x); aqan(x)=integrate(1/(x^4+1)^(1/2), x); acqn(x)=-integrate(1/(1+x^4)^(1/2), x); a constancy noted sigma sigma=(Gamma(1/4))^2/(2*sqrt(Pi)); some special points. qos(0)=1 ; qin(0)=0 ; qos(sigma/2)=0; qin(sigma/2)=1; qos(sigma)=-1; qin(sigma)=0; qos(sigma/4)=1/2^(1/4); qin(sigma/4)=1/2^(1/4); qan(sigma/4)=1; some integrals integrate(1/sqrt(x^4+1), x= 0.. 1)=sigma/4; integrate(1/(1-x^4)^(3/4),x=0..1/2^(1/4))=sigma/4; integrate(1/(1-x^4)^(3/4),x=0..1)=sigma/2; integrate(1/(1-x^4)^(3/4),x=-1..1)=sigma; FME...

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[math-fun] Eisenstein representation
by Fred Lunnon 24 Apr '18

24 Apr '18

There exists an algorithm for finding integers m,n such that x = m^2 + n^2 , in amortised time proportional to (log x)^3 , where x is prime with x mod 4 = 1 . See Richard E. Crandall, Carl Pomerance "Prime Numbers: A Computational Perspective" Springer (2001), sect 2.3.2 pp 93--96 . Is there an analogous efficient algorithm for x = m^2 + m n + n^2 ? See https://en.wikipedia.org/wiki/Eisenstein_integer https://oeis.org/A034017 , https://oeis.org/A000086 What about more general binary quadratic forms? Fred Lunnon

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Re: [math-fun] Radial disk-dissection
by Dan Asimov 22 Apr '18

22 Apr '18

I'm trying to guess what RWG meant without peeking at his drawings. In order to make Jim Propp's statement exact, I would have to make precise 1) what "dissect and reassemble" mean and 2) what "converges" to a 1-by-pi rectangle means. A typical meaning for 1): For subsets A, B of R^2, to dissect A and reassemble it to B means that there is a partition A = X_1 + ... + X_n of A as a finite disjoint union, such that there exist isometries f_1, ..., f_n of R^2 such that B = f_1(X_1) + ... + f_n(X_n) forms a partition of B as a finite disjoint union. * * * One meaning for 2) could be in the sense of Hausdorff distance between compact sets in the plane. The only problem I see here is that if strict partition are used in 1) as above, then the resulting rectangle B will not be compact, as it will not contain all of its boundary. I have complete faith that appropriate hand-waving will not incur the wrath of the math gods. —Dan ----- Jim Propp wrote: > If you dissect a unit disk radially into a large number of equal wedges, > it’s well known that you can reassemble them to form a shape that in the > limit converges to a 1-by-pi rectangle. > RWG wrote: ----- gosper.org/picfzoom.gif gosper.org/semizoom.gif --rwg I don't see how to get anything other than allowing unequal wedges. ----- -----

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Re: [math-fun] Optimally sorting a cyclic group
by Henry Baker 22 Apr '18

22 Apr '18

I don't know much about Sparc register banks, except that they seem to be "architectural" features -- i.e., something that the compiler has to know about in order to generate code that computes the correct answer -- rather than "performance" features -- i.e., something that the compiler *optimizers* have to know about in order to generate fast(er) code. At least a decade before the Sparc, there were "real time" microprocessors -- e.g., RCA's COSMAC/180X 8-bit processors -- where the "registers" were merely locations in external RAM selected by a special index register (at least in some implementations). Thus, although the compiler thought in terms of "registers", these registers didn't have faster access than any other RAM location. The reasons for this design: 1) very low interrupt latency: simply drop in a new register "index" and you instantly have a brand-new set of registers; and 2) not very much space on the chip for even one register bank, much less several -- these were very early single chip microprocessors. WRT patterns of cache behavior: We talked about n^(-1.5) "long tail" behavior for caches in the past several months. This "-1.5" exponent appears to be in the middle of the range for actual programs, so I'm taking this as a "given", at least for the moment. At 09:01 AM 4/22/2018, Tomas Rokicki wrote: >I was always intrigued by the SPARC register banks and how they compare >to just using the Tomasulo algorithm directly with fast caches . . . has anyone >looked at RISC V enough to determine if it uses register windows? > >Henry, I'm still struggling to understand precisely what patterns you see that >might be pre-existing in order to gain a benefit in sort time. Few of the n! >permutations have sufficient elements in-place (even when considering all >cyclic end-states) to make this interesting up front so you must have some >sort of permutation distribution in mind for which this might be a benefit. > >-tom > >On Fri, Apr 20, 2018 at 9:48 PM, Andres Valloud <avalloud(a)smalltalk.comcastbiz.net> wrote: > >> Starts sounding like SPARC's register banks / windows. >> >> How would software discover what the machine is doing to self-tune? >> >> On 4/20/18 14:30 , Henry Baker wrote: >>> Agreed. >>> >>> Blind men & elephants come from designing & evaluating >>> at the same time. >>> >>> I'm trying to figure out what major mechanisms are required >>> to achieve "essentially" optimal results w/o overdesigning. >>> >>> E.g., I've been resisting allowing "massive" simultaneous >>> rearrangements, but they may be required in order that >>> worst-case behavior doesn't dominate the average case >>> behavior. >>> >>> Why I'm doing this: I've been unhappy with the standard >>> RAM model which assumes constant memory access time for >>> all memory accesses, which is complete hogwash. >>> >>> What I'm really trying to design/model here is a memory >>> "cache", but a bizarre type of cache in that every cache >>> line has a slightly different access time, with more >>> "remote" elements being monotonically slower than "closer" >>> elements. As in modern microprocessors, the speed of >>> the fastest cache lines may be 3 orders of magnitude >>> faster than the slowest cache lines. Furthermore, the >>> cost of a cache line is directly correlated with its >>> speed, so there are far more slower elements than faster >>> ones. >>> >>> I haven't settled down on a particular cost model, >>> because I wanted to play with different cost models. >>> >>> As usual, we want most of the "work" to be done in >>> the closest/fastest cache lines, including any work >>> of rearranging the order of the cache lines. This >>> is because "small" rearrangements can be much faster >>> than "large" rearrangements. >>> >>> These are all "exclusive" caches, meaning that a >>> particular item lives in exactly one cache line. >>> >>> I think I'm close to deciding that some massive >>> rearrangements -- e.g., replacing the first N elements >>> of the fastest part of the cache with N sequential >>> remote elements -- will be a necessary builtin feature. >>> However, it is likely that the cost of such a massive >>> rearrangement will have to be correlated with the >>> "distance" as well as the number of items. Furthermore, >>> it may be necessary and/or convenient to have the >>> number of elements (N) involved in each transfer be >>> correlated with the distance. There is a tradeoff >>> here because a large transfer from "far" may bring >>> in something you need, but also a lot of other stuff >>> you did't want -- thus "polluting" the fast cache. >>> >>> This is reminiscent of 1950's/1960's style programming >>> where large blocks of data have to be brought in/out by >>> "channel operations"; some of these channels were even >>> smart enough to transfer data *within* main memory w/o >>> even touching an I/O device. >>> >>> At 12:44 PM 4/20/2018, Tomas Rokicki wrote: >>> >>>> I think we need some sort of explicit cost model here. Otherwise we are >>>> each blindly touching a different part of the elephant. >-- >-- http://cube20.org/ -- http://golly.sf.net/ --

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Re: [math-fun] Optimally sorting a cyclic group
by Henry Baker 22 Apr '18

22 Apr '18

Agreed. Blind men & elephants come from designing & evaluating at the same time. I'm trying to figure out what major mechanisms are required to achieve "essentially" optimal results w/o overdesigning. E.g., I've been resisting allowing "massive" simultaneous rearrangements, but they may be required in order that worst-case behavior doesn't dominate the average case behavior. Why I'm doing this: I've been unhappy with the standard RAM model which assumes constant memory access time for all memory accesses, which is complete hogwash. What I'm really trying to design/model here is a memory "cache", but a bizarre type of cache in that every cache line has a slightly different access time, with more "remote" elements being monotonically slower than "closer" elements. As in modern microprocessors, the speed of the fastest cache lines may be 3 orders of magnitude faster than the slowest cache lines. Furthermore, the cost of a cache line is directly correlated with its speed, so there are far more slower elements than faster ones. I haven't settled down on a particular cost model, because I wanted to play with different cost models. As usual, we want most of the "work" to be done in the closest/fastest cache lines, including any work of rearranging the order of the cache lines. This is because "small" rearrangements can be much faster than "large" rearrangements. These are all "exclusive" caches, meaning that a particular item lives in exactly one cache line. I think I'm close to deciding that some massive rearrangements -- e.g., replacing the first N elements of the fastest part of the cache with N sequential remote elements -- will be a necessary builtin feature. However, it is likely that the cost of such a massive rearrangement will have to be correlated with the "distance" as well as the number of items. Furthermore, it may be necessary and/or convenient to have the number of elements (N) involved in each transfer be correlated with the distance. There is a tradeoff here because a large transfer from "far" may bring in something you need, but also a lot of other stuff you did't want -- thus "polluting" the fast cache. This is reminiscent of 1950's/1960's style programming where large blocks of data have to be brought in/out by "channel operations"; some of these channels were even smart enough to transfer data *within* main memory w/o even touching an I/O device. At 12:44 PM 4/20/2018, Tomas Rokicki wrote: >I think we need some sort of explicit cost model here. Otherwise we are >each blindly touching a different part of the elephant.

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Re: [math-fun] Nearest Rational Algorithm
by Guy Haworth 22 Apr '18

22 Apr '18

Thanks, James B ... interesting how infrequent the 'improved approximations' are. Guy

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[math-fun] Nearest rationals algorithm
by Guy Haworth 22 Apr '18

22 Apr '18

I think there was a discussion about 'nearest rationals to pi' ... and I think there's a 'sequence' about that somewhere. I'd be interested in an algorithm to generate such sequences, ... and I'd like to see what results it gives for sqrt(2)^sqrt(2) ... a number which has a specific role in proving that a^b can be rational even if 'a' and 'b' are not [see, e.g., The Princeton Companion] Guy

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